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DM9161B
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
39 Final
Version: DM9161B-12-DS-F01
January 31, 2008
9.4.10 MII 100BASE-TX Receive Timing Diagram
RXCLK
t
2
t
1
t
TX
pd
RXD [0:3],
RXDV, RXER
CRS
RX+/-
t
RX
S
t
RX
h
t
4
t
3
COL
t
5
t
5
tRXctRXh
9.4.11 MII 10BASE-T Nibble Transmit Timing Parameters
Symbol Parameter Min. Typ. Max. Unit Conditions
tTX
s
TXD[0:3), TXEN, TXER Setup To TXCLK High 5 - - ns
tTX
h
TXD[0:3], TXEN, TXER Hold From TXCLK High 5 - - ns
t1 TXEN Sampled To CRS Asserted - 2 4 BT
t2 TXEN Sampled To CRS De-asserted - 15 20 BT
tTX
pd
TXEN Sampled To 10TXO Out (Tx Latency) - 2 4 BT
9.4.12 MII 10BASE-T Nibble Transmit Timing Diagram
TXCLK
t
TX
h
t
2
t
TX
S
t
1
t
TX
pd
TXD [0:3],
TXEN, TXER
CRS
10TX+/-