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YMF715E
May 21, 1997
-7-
1-2. Pin description
SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7
MP0 - /MCS /MCS /EXTEN /EXTEN /MCS - /EXTEN
MP1 - MIRQ MIRQ /SYNCS /SYNCS MIRQ - /SYNCS
MP2 - ROMCLK ROMCLK ROMCLK BCLK_ZV A12 - A12
MP3 - ROMCS ROMCS ROMCS LRCK_ZV A13 - A13
MP4 - ROMDI ROMDI ROMDI SIN_ZV A14 - A14
MP5 - ROMDO ROMDO ROMDO /XRST A15 - A15
MP6 - /CDCS0 A12 BCLK_ML BCLK_ML BCLK_ZV - BCLK_ML
MP7 - /CDCS1 A13 LRCK_ML LRCK_ML LRCK_ZV - LRCK_ML
MP8 - CDIRQ A14 SIN_ML SIN_ML SIN_ZV - SIN_ML
MP9 - CLKO A15 CLKO CLKO /XRST - CLKO
Note : do not select SEL=0 and SEL=6.
SEL=0 ; TEST mode SEL=6 ; reserved
Mutil-
p
ur
p
ose
p
ins:
name I/O function
/MCS O Chi
p
select out
p
ut for MODEM chi
p
(
COM
)
MIR
Q
I+ Interru
p
t re
q
uest in
p
ut for MODEM
(
COM
)
ROMCLK O Serial data clock out
p
ut for external EEPROM
ROMCS O Chi
p
select out
p
ut for external EEPROM
ROMDI I+ Serial data in
p
ut for external EEPROM
ROMDO O Serial data out
p
ut for external EEPROM
/CDCS0 O Chi
p
select out
p
ut for IDE CD-ROM
(
/CS1FX
)
/CDCS1 O Chi
p
select out
p
ut for IDE CD-ROM
(
/CS3FX
)
CDIR
Q
I+ Interru
p
t re
q
uest in
p
ut for IDE CD-ROM
A12 - 15 I Address bus for ISA-bus
/EXTEN I+ Enable OPL4-ML/ML2 interface
/SYNCS O Chi
p
select out
p
ut for OPL4-ML/ML2
BCLK_ML I+ Bit clock in
p
ut for OPL4-ML/ML2
LRCK_ML I+ L/R clock in
p
ut for OPL4-ML/ML2
SIN_ML I+ Serial data in
p
ut for OPL4-ML/ML2
CLKO O Master clock out
p
ut
(
33.8688MHz
)
BCLK_ZV I+ Bit clock in
p
ut for Zoomed Video
p
ort
(
I
2
S
)
LRCK_ZV I+ L/R clock in
p
ut for Zoomed Video
p
ort
(
I
2
S
)
SIN_ZV I+ Serial data in
p
ut for Zoomed Video
p
ort
(
I
2
S
)
/XRST O Inverted RESET out
p
ut