EMAC Control Module Registers
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3.8 EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers
(C0RXTHRESHSTAT-C2RXTHRESHSTAT)
The EMAC control module interrupt core 0-2 receive threshold interrupt status register
(CnRXTHRESHSTAT) is shown in Figure 19 and described in Table 16
Figure 19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RXCH7THRESH RXCH6THRESH RXCH5THRESH RXCH4THRESH RXCH3THRESH RXCH2THRESH RXCH1THRESH RXCH0THRESH
STAT STAT STAT STAT STAT STAT STAT STAT
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT)
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RXCH7THRESHSTAT Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register
0 RX Channel 7 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 7 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
6 RXCH6THRESHSTAT Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register
0 RX Channel 6 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 6 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
5 RXCH5THRESHSTAT Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register
0 RX Channel 5 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 5 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
4 RXCH4THRESHSTAT Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register
0 RX Channel 4 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 4 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
3 RXCH3THRESHSTAT Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register
0 RX Channel 3 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 3 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
2 RXCH2THRESHSTAT Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register
0 RX Channel 2 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 2 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
1 RXCH1THRESHSTAT Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register
0 RX Channel 1 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 1 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
0 RXCH0THRESHSTAT Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register
0 RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.
1 RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.
64
EMAC/MDIO Module SPRUFL5B–April 2011
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