98 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Arbitration
10.3 Primary PCI Bus Arbitration
The 21555 implements primary PCI bus request and grant pins, p_req_l and p_gnt_l, that interface to an external
primary bus arbiter. These pins are used when the 21555 wants to initiate a transaction on the primary PCI bus.
The 21555 asserts p_req_l when a posted write or delayed transaction is queued in upstream buffers. Signal
p_req_l remains asserted as long as the posted write and delayed transaction queues contain pending transactions;
otherwise, p_req_l is deasserted two cycles after the address phase. However, when the 21555 keeps p_req_l
asserted and the 21555 detects a target retry or target disconnect in response to an ongoing transaction, it deasserts
p_req_l one cycle after detecting that p_stop_l is asserted before reattempting arbitration for that transaction. The
signal p_req_l is deasserted for two clock cycles.
When a prefetchable read is ongoing on the primary bus when another delayed read is queued behind it, the 21555
delays the assertion of p_req_l. The assertion of p_req_1 is delayed until the 21555 is ensured that there is room in
the read data queue for the second delayed read transaction.
When p_gnt_l is asserted when p_req_l is not asserted, the 21555 parks p_ad, p_cbe_l, and p_par by driving
them to valid logic levels. The 64-bit extension signals are not parked. When the primary bus is parked at the
21555, and the 21555 has a transaction to initiate on the primary bus, it starts the transaction immediately as long as
p_gnt_l was asserted during the previous clock cycle.
10.4 Secondary PCI Bus Arbitration
The 21555 implements an internal secondary PCI bus arbiter supporting nine secondary bus masters, plus the
21555. The internal arbiter may be disabled and an external arbiter used for secondary bus arbitration.
The behavior of the 21555 secondary request is identical to the behavior of the 21555’s primary bus request.
10.4.1 Secondary Bus Arbitration Using the Internal Arbiter
The 21555 enables the secondary bus arbiter when it detects pr_ad[7] high during reset. The 21555 has nine
secondary bus request input pins, s_req_l[8:0], and nine secondary bus output grant pins, s_gnt_l[8:0], to support
external secondary bus masters. The 21555 secondary bus request and grant signals are connected internally to the
arbiter and are not brought out to external pins when the arbiter is enabled. The minimum latency between
secondary bus request assertion and secondary bus grant assertion is two clock cycles.
The secondary arbiter supports a programmable two level rotating priority algorithm. Two groups of masters are
assigned, a high priority group and a low priority group. The low priority group as a whole represents one entry in
the high priority group. That is, when the high priority group consists of N masters, then in at least every N+1
transactions the highest priority is assigned to the low priority group. Priority rotates evenly among the low priority
group. Therefore, members of the high priority group can be serviced N transactions out of N+1, while one member
of the low priority group is serviced once every N+1 transactions.
Figure 25 is an example where four masters, including the 21555, are in the high priority group and six masters are
in the low priority group.
When all requests are asserted, the highest priority rotate among the masters in the following fashion (high priority
members in italics, low priority members in bold):
B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1,... etc.
