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15
Performance Characteristics (continued)
Vertical System: Digital Channels (54621D, 54622D, 54641D, and 54642D only)
Number of Channels 16 Digital – labeled D15 - D0
Threshold Groupings Pod 1: D7 - D0
Pod 2: D15 - D8
Threshold Selections TTL, CMOS, ECL, user-definable (selectable by pod)
User-Defined Threshold Range ±8.0 V in 10 mV increments
Maximum Input Voltage ±40 V peak CAT I
Threshold Accuracy* ±(100 mV + 3% of threshold setting)
Input Dynamic Range ±10 V about threshold
Minimum Input Voltage Swing 500 mV peak-to-peak
Input Capacitance ~ 8 pF
Input Resistance 100 kΩ ±2% at probe tip
Channel-to-Channel Skew 2 ns typical, 3 ns maximum
Horizontal
Range 54621A/D, 54622A/D, 54624A: 5 ns/div to 50 s/div
54641A/D, 54642A/D: 1 ns/div to 50 s/div
Resolution 54621A/D, 54622A/D, 54624A: 25 ps
54641A/D, 54642A/D: 2.5 ps
Vernier 1-2-5 increments when off, ~25 minor increments between major settings when on
Reference Positions Left, Center, Right
Delay Range 54621A/D, 54622A/D, 54624A:
Pre-trigger (negative delay): Greater of 1 screen width or 10 ms
Post-trigger (positive delay): 500 seconds
54641A/D, 54642A/D:
Pre-trigger (negative delay): Greater of 1 screen width or 1 ms
Post-trigger (positive delay): 500 seconds
Analog Delta-t Accuracy 54621A/D, 54622A/D, 54624A:
Same Channel*: ±0.01% reading ±0.1% screen width ±40 ps
Channel-to-Channel: ±0.01% reading ±0.1% screen width ±80 ps
54641A/D, 54642A/D:
Same Channel*: ±0.005% reading ±0.1% screen width ±20 ps
Channel-to-Channel: ±0.005% reading ±0.1% screen width ±40 ps
Same Channel Example (54641A/D, 54642A/D):
for signal with pulse width of 10 µs, scope set to 5 µs/div (50 µs screen width),
delta-t accuracy = ±{.005%(10 µs) + 0.1%(50 µs) + 20 ps} = 50.52 ns
* Denotes Warranted Specifications, all others are typical. Specifications are valid after a 30-minute warm-up period and ±10 °C from firmware calibration temperature.